AMD Geode SC3200 manuels

Amd Geode SC3200 Manuel d'utilisateur (428 pages)

marque: Amd | Catégorie: Cartes mères | Taille: 3.26 MB |

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Table des matières

AMD Geode™ SC3200 Processor

1

Data Book

1

Contents

3

List of Figures

5

List of Tables

10

1.0Overview

13

1.2 Features

14

Overview

16

2.0Architecture Overview

17

2.2 Video Processor Module

22

2.3 Core Logic Module

22

2.4 Super I/O Module

23

Architecture Overview

24

3.0Signal Definitions

25

Signal Definitions

26

3.1 Ball Assignments

27

AMD Geode™

28

SC3200 Processor

28

3.2 Strap Options

44

3.4 Signal Descriptions

49

3.4.4 TFT Interface Signals

52

3.4.9 IDE Interface Signals

58

3.4.16 GPIO Interface Signals

65

Reserved - RSVD

76

4.3 WATCHDOG

77

4.3.2 WATCHDOG Registers

78

4.4 High-Resolution Timer

79

4.5 Clock Generators and PLLs

81

Circuitry

82

Default ADL Multiplier

83

0111 33.33 4 0100 133

83

4.5.4 SuperI/O Clocks

84

4.5.6 Video Processor Clocks

84

5.0SuperI/O Module

87

5.1 Features

88

5.2 Module Architecture

89

5.3.4 Address Decoding

91

Configuration

96

5.5 Real-Time Clock (RTC)

103

SuperI/O Module

105

5.5.3 RTC Registers

109

Table 5-19. RTC Register Map

109

Table 5-20. RTC Registers

109

Table 5-25. Extended RAM Map

113

Table 5-24. Standard RAM Map

113

5.6.1 Event Detection

114

Type Name

115

Type Name

115

5.7 ACCESS.bus Interface

119

5.7.3 Acknowledge (ACK) Cycle

120

5.7.6 Arbitration on the Bus

121

5.7.7 Master Mode

121

5.7.8 Slave Mode

123

5.7.9 Configuration

123

5.8 Legacy Functional Blocks

127

Offset Name

128

404h EDR Data Bits

128

Architecture

129

Table 5-42. Bank 0 Bit Map

131

Table 5-43. Bank 1 Bit Map

131

Table 5-44. Bank 2 Bit Map

132

Table 5-45. Bank 3 Bit Map

132

Port 3 (SP3) Functionality

133

Table 5-56. Bank 1 Bit Map

137

Table 5-57. Bank 2 Bit Map

137

Table 5-58. Bank 3 Bit Map

137

Table 5-59. Bank 4 Bit Map

137

Table 5-60. Bank 5 Bit Map

138

Table 5-61. Bank 6 Bit Map

138

Table 5-62. Bank 7 Bit Map

138

6.0Core Logic Module

139

6.2 Module Architecture

140

6.2.2 PSERIAL Interface

141

6.2.3 IDE Controller

142

Core Logic Module

144

6.2.4 Universal Serial Bus

145

6.2.5 Sub-ISA Bus Interface

145

6.2.6 AT Compatibility Logic

150

Figure 6-7. PIT Timer

152

6.2.8 Keyboard Support

155

C1 Power State - Active Idle

156

Sleep States

158

6.2.11 GPIO Interface

165

6.2.12 Integrated Audio

165

SMI# (System Management

169

Read to Clear

170

Figure 6-15. Typical Setup

171

Table 6-12. Cycle Types

172

6.3 Register Descriptions

173

6.3.2 Register Summary

174

6.4 Chipset Register Space

188

CPI mode

201

20h and 24h)

220

1), this bit allows signal

229

]. Reading

239

15:6 Reserved

239

Not Used Reset Value: 00h

244

31:24 Reserved

254

Reserved Reset Value: 00h

254

0 Reserved. (Read Only)

261

Not Used

270

00h/02h[14]

280

Bit Description

283

Reserved Reset Value = xxh

293

7.0Video Processor Module

309

7.1 Module Architecture

310

7.2 Functional Description

311

(Not normally User Data)

312

Figure 7-4. VIP Block Diagram

313

Video Processor Module

314

7.2.2 Video Block

317

7.2.3 Mixer/Blender Block

320

[20:16])

322

Windows Configuration

323

7.2.4 TFT Interface

325

7.2.5 Integrated PLL

326

7.3 Register Descriptions

327

]) is an

338

8.0Debugging and Monitoring

349

Debugging and Monitoring

350

9.0Electrical Specifications

351

9.1.4 Operating Conditions

352

9.1.5 DC Current

353

Electrical Specifications

354

9.2 DC Characteristics

357

9.3 AC Characteristics

362

AMD Geode™ GX1 Proces

364

9.3.2 Video Port

366

9.3.3 TFT Interface

367

9.3.4 ACCESS.bus Interface

368

Note 2. t

369

Ω1 KΩ 10 pF

371

Figure 9-18. PCI Reset Timing

376

9.3.6 Sub-ISA Interface

377

9.3.7 LPC Interface

381

9.3.8 IDE Interface

382

9.3.11 Fast IR Port

405

9.3.13 Audio Interface (AC97)

410

9.3.15 Power-Up Sequencing

416

9.3.16 JTAG Interface

418

10.0Package Specifications

421

Figure 10-1. Heatsink Example

422

10.2 Physical Dimensions

423

Package Specifications

424

A.1 Order Information

425

Table A-1. Revision History

426

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